Ruthenium<\/a> is a leading candidate, but it\u2019s not as simple as swapping one metal for another, according to research reported at IEDM 2022. The processes of how they\u2019re formed on a chip must be turned upside down. These new interconnects will need a different shape and a higher density. These new interconnects will also need better insulation, lest signal-sapping capacitance take away all their advantage.<\/p>\n Even where the interconnects go is set to change, and soon. But studies are starting to show, the gains from that shift come with a certain cost.<\/p>\n Among the replacements for copper, ruthenium has gained a following. But research is showing that the old formulas used to build copper interconnects are a disadvantage to ruthenium. Copper interconnects are built using what\u2019s called a damascene process<\/a>. First chip makers use lithography to carve the shape of the interconnect into the dielectric insulation above the transistors. Then they deposit a liner and a barrier material, which prevents copper atoms from drifting out into the rest of the chip to muck things up. Copper then fills the trench. In fact, it overfills it, so the excess must be polished away.<\/p>\n All that extra stuff, the liner and barrier, take up space, as much as 40-50 percent of the interconnect volume, Penny told engineers at IEDM. So the conductive part of the interconnects are narrowing, especially in the ultrafine vertical connections between layers of interconnects, increasing resistance. But IBM and Samsung researchers have found a way to build tightly-spaced, low-resistance ruthenium interconnects that don\u2019t need a liner or a seed. The process is called spacer assisted litho-etch litho-etch, or SALELE<\/a>, and, as the name implies, it relies on a double helping of extreme-ultraviolet lithography<\/a>. Instead of filling in trenches, it etches the ruthenium interconnects out of a layer or metal and then fills in the gaps with dielectric.<\/p>\n The researchers achieve the best resistance using tall, thin horizontal interconnects. However, that increases capacitance, trading away the benefit. Fortunately, due to the way SALELE builds vertical connections called vias<\/a>\u2014on top of horizontal interconnects instead of beneath them\u2014the spaces between slender ruthenium lines can easily be filled with air, which is the best insulator available. For these tall, narrow interconnects \u201cthe potential benefit of adding an air gap is huge\u2026 as much as a 30 percent line capacitance reduction,\u201d said Penny.<\/p>\n The SALELE process \u201cprovides a roadmap to 1-nanometer processes and beyond,\u201d he said.<\/p>\n As early as 2024, Intel plans<\/a> to make a radical change to the location of interconnects that carry power to transistors on a chip. The scheme, called back-side power delivery<\/a>, takes the network of power delivery interconnects and moves it beneath the silicon, so they approach the transistors from below. This has two main advantages: It allows electricity to flow through wider, less resistive interconnects, leading to less power loss. And it frees up room above the transistors for signal-carrying interconnects, meaning logic cells can be smaller. (Researchers from Arm and the Belgian nanotech research hub Imec<\/a> explained it all here<\/a>.)<\/p>\nRuthenium, top vias, and air gaps<\/h2>\n
Buried rails, back-side power delivery, and hot 3D chips<\/h2>\n
![\"Many](\"https:\/\/spectrum.ieee.org\/media-library\/many-colored-columns-extending-between-grey-horizontal-slabs.jpg?id=32417179&width=980\")
Researchers tested a scenario where a CPU [bottom grey] with a back-side power delivery network is bonded to a second CPU having a front-side power delivery network [top grey].<\/small><\/p>\n